Various mechanisms exist that allow the integrity of a particular computing device and/or particular components of the computing device to be confirmed. For example, computing devices often implement a power-on self-test (POST) procedure in order to test the memory, buses, and/or other components on power-up. Similarly, a built-in self-test (BIST) mechanism may be utilized to verify the internal functionality of an integrated circuit. Generally, BIST mechanisms output one or more cyclic redundancy check (CRC) values that may be compared to reference values associated with a properly functioning integrated circuit.
BIST mechanisms are often used to check for errors made during manufacturing. For example, if a transistor of an integrated circuit is “popped” or a wire/trace is not properly connected during manufacturing, the CRC value outputted by the BIST mechanism will vary from that of the integrated circuit when properly constructed and properly functioning. As such, BIST mechanisms are generally intended to address statistically randomly distributed errors associated with manufacturing and do little to attest to the security of the integrated circuit. For example, it is conceivable that an attacker could remove some circuitry from the integrated circuit and achieve the same BIST CRC values as with the properly functioning circuit (e.g., due to collision associated with CRC functions).